Conventionally, a frequency synthesizer using a PLL is widely used in radio communication device and tuner. FIG. 1 is a configuration diagram of a general frequency synthesizer using a PLL. The frequency synthesizer shown in FIG. 1 includes a reference oscillator circuit 1 that generates a reference clock 14, a phase comparator circuit 2 that detects the phase difference between the reference clock 14 and a feedback clock 15 and that outputs a pulse corresponding to the phase difference, a low-pass filter (LPF) 3 that smoothes the pulse outputted from the phase comparator circuit 2 and generates a control voltage signal 11, a voltage-control led oscillator (VCO) group 95 in which a plurality of voltage-controlled oscillators (VCO) that oscillate at an oscillation frequency that depends on the control voltage signal 11 are provided, and a frequency divider circuit 4 that divides the frequency of an output signal 10 generated by the voltage-controlled oscillator (VCO) group 95 and generates the feedback clock 15. When the phase difference between the reference clock 14 and the feedback clock 15 is detected, whether or not the phase difference is stably within a predetermined range is also detected. In the case where the phase difference is stably within the predetermined range, the frequency synthesizer further comprises a lock detector (LD) 6 that outputs a lock detection signal 18 to the outside. Further, this frequency synthesizer is provided in a tuner IC 75 and is connected to a base band IC 76 via a bus interface such as an 12C (Inter-Integrated Circuit) bus.
Next, the structure of the voltage-controlled oscillator (VCO) group 95 will be described in detail. The voltage-controlled oscillator (VCO) group 95 includes a plurality of voltage-controlled oscillators with different characteristics such as the range of the oscillation frequency. A voltage-controlled oscillator is comprised of a plurality of capacitance elements, a negative resistance portion 50, and an inductor 51. The plurality of capacitance elements are constituted by a plurality of fixed capacitances connected in parallel to each other and respectively on/off controlled by switches 58, 59, and 60, a variable capacitance diode (varactor for fine-tuning the frequency) 52 whose DC bias voltage is controlled by the control voltage signal 11, and a fixed capacitance 55 connected to the variable capacitance diode 52 in series. The capacitance value of the voltage-controlled oscillator is roughly determined by the aforementioned switches. The oscillation frequency is determined by fine-tuning the capacitance value using the voltage value of the control voltage signal.
Further, a VCO automatic control block 7 selects one voltage-controlled oscillator from the plurality of VCOs and turns on/off the switches that determine the approximate capacitance value, based on a command sent from the base band IC 76 via the bus.
Next, the procedure in which the VCO automatic control block 7 changes the oscillation frequency and locks it will be described with reference to FIG. 1 and a timing chart shown in FIG. 2. When the oscillation frequency needs to be changed, first, the base band IC 76 sends a command, such as the channel to be changed, for the voltage-controlled oscillator (VCO) group 95 to the VCO automatic control block 7. Based on the command, the VCO automatic control block 7 performs the selection of a voltage-controlled oscillator and the switches that turn on/off the fixed capacitance. Next, the PLL loop is pulled in based on this setting. The phase comparator circuit 2 detects the phase difference between the reference clock 14 and the feedback clock 15, and the low-pass filter 3 changes this phase difference into the control voltage signal 11 for the variable capacitance diode 52, automatically adjusting the capacitance value of the variable capacitance diode. Finally, oscillation is performed at a stable frequency and a locked state is established. Time t required from start of setting channel to oscillating in a stable locked state is 1 to 3 ms.
A frequency synthesizer designed to shorten the channel switching time is disclosed in Patent Document 1. The frequency synthesizer disclosed in Patent Document 1 will be described with reference to the drawings. FIG. 3 is a drawing showing the configuration of the frequency synthesizer. This frequency synthesizer comprises three variable capacitance diodes. A DA converter 80 supplies a DC bias voltage to the first variable capacitance diode 41, which is serially connected to a fixed capacitance 42 and determines the approximate capacitance value of a voltage-controlled oscillator 34. The variable capacitance diode 41 provides a similar function to that of the fixed capacitances turned on/off by the switches 58 to 60, shown in FIG. 1. Compared to the conventional example in FIG. 1, the range of capacitance adjustable by the variable capacitance diode 41 is smaller. However, because of this, it is possible to fine-tune the capacitance value even further and the time it takes from the channel switching to the loop acquisition is shortened.
Next, the second variable capacitance diode 44 receives a control voltage signal from a low-pass filter and is serially connected to a fixed capacitance 45. The variable capacitance diode 44 has the same function as the variable capacitance diode 52 serially connected to the fixed capacitance 55 in FIG. 1. The third variable capacitance diode 47 is provided so that it immediately reestablishes a locked state with the help of operational amplifiers 35 and 36 and rectifier diodes 37 and 38 when the lock is released for some reason even though the channel has not been changed.
Further, Patent Document 2 describes a PLL frequency synthesizer in which the time it takes to establish a locked state is shortened by widening the variable range of the oscillation frequency of the voltage-controlled oscillator in an unlocked state and oscillation with low phase noise is realized by narrowing the variable range of the oscillation frequency of the voltage-controlled oscillator after a locked state has been established.
Further, Patent Document 3 discloses a frequency synthesizer in which the DC bias voltage applied to the variable capacitance diode and the temperature compensation digital value are stored in a memory in advance so that a predetermined frequency will oscillate and characteristic changes caused by aged deterioration and the temperature characteristics are compensated.
Further, Patent Document 4 discloses a PLL comprising a voltage-controlled oscillator that switches an oscillation band using a digital signal supplied by a control terminal.
[Patent Document 1]
    Japanese Patent Kokai Publication No. JP-A-6-326604[Patent Document 2]    Japanese Patent Kokai Publication No. JP-P2007-13898A[Patent Document 3]    Japanese Patent Kokai Publication No. JP-U-6-19327[Patent Document 4]    Japanese Patent Kokai Publication No. JP-A-10-051304